Method of manufacturing semiconductor devices using a capping layer in forming gate electrode and semiconductor devices
US11081584B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Aug 5, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Aug 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.