Multi-gate transistor and memory device using the same
US11081595B1 · kind B1 · utility
2Cited by
3References
9Claims
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Key dates
| Filing date | May 19, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | May 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.