Decoders for analog neural memory in deep learning artificial neural network
US11087207B2 · kind B2 · utility
7Cited by
22References
36Claims
0Family size
Assignee
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Key dates
| Filing date | May 29, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Jun 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.