Transistor structure
US11088027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Sep 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.