Method of forming a multi-level interconnect structure in a semiconductor device
US11088070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Jul 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.