4Cpp SRAM cell and array
US11088151B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Oct 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.