Method for fabricating split-gate non-volatile memory
US11088155B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Apr 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for fabricating split-gate non-volatile memory. The method comprises the following: 1) preparing a semiconductor substrate by forming at least one shallow trench isolation structure in the semiconductor substrate to isolate at least one active region in the semiconductor substrate; 2) forming at least one word line on the semiconductor substrate; 3) forming at least one source and at least one drain in the semiconductor substrate, and forming at least one floating gate on a sidewall of the word line on a side close to the source; 4) removing part of the word line by adopting an etching process; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming at least one metal bit line on the conductive plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.