3D RRAM cell structure for reducing forming and set voltages
US11088203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Sep 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.