Method of forming multiple-Vt FETs for CMOS circuit applications
US11088258B2 · kind B2 · utility
1Cited by
21References
20Claims
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Key dates
| Filing date | Feb 26, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.