Pulsed flip-flop capable of being implemented across multiple voltage domains
US11088678B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.