Calibrating internal pulses in an integrated circuit
US11088684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.