Semiconductor memory device
US11093172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Oct 21, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.