Patent · US Active

Domino full adder based on delayed gating positive feedback

US11093214B2 · kind B2 · utility

0Cited by

1References

1Claims

0Family size

Assignee

Ningbo University · CN

Inventors

Pengjun Wang · Zhejiang, CN
Xiaotian Zhang · San Jose, US
Huihong Zhang · Zhejiang, CN
Yuejun Zhang · Zhejiang, CN
Haizhen Yu · Zhejiang, CN

Key dates

Filing date	Oct 13, 2020
Grant date	Aug 17, 2021
Priority date	—
Expiry date	Oct 13, 2040

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.