High parallelism computing system and instruction scheduling method thereof
US11093225B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Jan 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high parallelism computing system and instruction scheduling method thereof are disclosed. The computing system comprises: an instruction reading and distribution module for reading a plurality of types of instructions in a specific order, and distributing the acquired instructions to corresponding function modules according to the types; an internal buffer for buffering data and instructions for performing computation; a plurality of function modules each of which sequentially executes instructions of the present type distributed by the instruction reading and distribution module and reads the data from the internal buffer; and wherein the specific order is obtained by topologically sorting the instructions according to a directed acyclic graph consisting of the types and dependency relationships. By reading the instructions based on the topological sorting the directed acyclic graph constructed according to the types and dependency relationships, the deadlock caused by the instruction dependencies can be avoided by a relatively simple operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.