Systems and methods to load a tile register pair
US11093247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.