Systems and methods to control semiconductor memory device in various timings
US11094366B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Feb 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a semiconductor memory device includes first and second memory cells and a controller. In a program operation, the controller applies a first voltage to a select gate line at a first timing, applies a second voltage to a select gate line at a second timing, applies a third voltage to a word line at a third timing, and applies a fifth voltage to a word line at a fifth timing. In a program operation when the first memory cell is selected, a time between the second timing and the third timing is a first time. In a program operation when the second memory cell is selected, a time between the second timing and the third timing is a second time different from the first time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.