Semiconductor structure and method for manufacturing the same
US11094578B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | May 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different. The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-layer stack and under the switch device. The air void is surrounded by dielectric filling material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.