Patent · US Active

System and method to enhance solder joint reliability

US11094604B2 · kind B2 · utility

0Cited by

3References

20Claims

0Family size

Assignee

Western Digital Technologies, Inc. · US

Inventors

Lee Kong Yu · Bukit Mertajam, MY
Sungjun Im · San Jose, US
Chun Sean Lau · Kampung Bukit Kechil, MY
Yoong Tatt Chin · Bukit Mertajam, MY
Paramjeet Singh Gill · Kuala Lumpur, MY
Weng Hong Teh · Phoenix, US

Key dates

Filing date	Jun 27, 2019
Grant date	Aug 17, 2021
Priority date	—
Expiry date	Jun 27, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3512
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.