Determining overlay of features of a memory array
US11094643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Apr 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses, and systems related to determining overlay of features of a memory array are described. An example method includes forming a plurality of contacts on a working surface and selectively forming a first portion of a layer of conductive lines and a second portion of the layer of conductive lines in contact with the contacts. The first portion of the layer of conductive lines formed over the working surface is separated from the second portion of the layer of conductive lines formed over the working surface by a gap. The method includes determining an overlay of at least one of the contacts formed over the working surface in the gap relative to one of the conductive lines formed over the working surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.