Layout structure of storage cell and method thereof
US11094701B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jul 17, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Jul 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.