Branch prediction circuitry comprising a return address prediction structure and a branch target buffer structure
US11099850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Aug 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.