Controller and memory system
US11099932B2 · kind B2 · utility
2Cited by
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7Claims
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Assignee
Inventor
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.