Multiplier-accumulator
US11100989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Jul 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operation section, memory cells storing respective synaptic connection weights are arranged in rows and columns. Output lines are connected to memory cells in the corresponding column, and input lines are connected to memory cells in the corresponding row. Each output line is precharged, and then its electric potential is decreased during the corresponding memory cells flow cell currents corresponding to their synaptic connection weights. A memory element of each memory cell includes a memory transistor, a drain side transistor, and a source side transistor connected in series, and is connected between the corresponding input and output line. The memory transistor stores a synaptic connection weight according to the amount of charge in a charge storage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.