Memory cell arrangement and methods thereof
US11101291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.