Back-side memory element with local memory select transistor
US11101318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | May 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.