Method for forming semiconductor device structure with metal silicide layer
US11101354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Aug 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.