Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors

US11101356B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Karthik Jambunathan · Hillsboro, US
• Cory Bomberger · Portland, US
• Tahir Ghani · Portland, US
• Jack T. Kavalieros · Portland, US
• Benjamin Chu-Kung · Portland, US
• Seung Hoon Sung · Beaverton, US
• Siddharth Chouksey · Portland, US

Key dates

• Filing date: Sep 29, 2017
• Grant date: Aug 24, 2021
• Expiry date: Sep 29, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.