Metal etching stop layer in magnetic tunnel junction memory cells
US11101429B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Apr 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.