Selective sampling of a data unit during a program erase cycle based on error rate change patterns
US11106532B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Apr 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.