Memory blockade for verifying system security with respect to speculative execution
US11106602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method includes generating a plurality of test cases to test exploitation of speculative execution in a design of a computer processor, where the plurality of test cases include a first test case. Generating the first test case includes identifying a branch responsive to an attempted access to secure data and, responsive to the branch, marking each memory address of each memory access dependent on the attempted access to the secure data. The computer-implemented method further includes executing the first test case. Executing the first test case includes detecting an attempt to access a memory address that has been marked and, responsive to the attempt to access the memory address that has been marked, alerting of a security violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.