Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device
US11107630B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | May 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N30/872
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.