Semiconductor manufacturing process

US11107699B2 · kind B2 · utility

Assignee

• BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD. · CN

Inventors

• Peijun Ding · San Jose, US
• Bo Zheng · Sunnyvale, US
• Zhenguo Ma · Beijing, CN
• Chun Wang · Beijing, CN
• Jing Shi · Beijing, CN
• Xin Wu · Beijing, CN
• Xiaojuan Wang · Cambridge, GB

Key dates

• Filing date: Dec 13, 2019
• Grant date: Aug 31, 2021
• Expiry date: Dec 13, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76243
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor manufacturing process is provided. A trench is formed in a semiconductor structure and an oxide layer is deposited on sidewalls of the trench. A solid-state by-product layer is formed on surfaces of the trench by introducing a first etchant gas to react with a naturally occurred oxide layer at the bottom of the trench and the deposited oxide layer. The solid-state by-product layer has a thickness on the bottom less than a thickness on the sidewalls. A second etchant gas is introduced into the trench to react with the solid-state by-product layer, thereby providing a thinned solid-state by-product layer on the sidewalls to protect the deposited oxide layer. By a heating process, the thinned solid-state by-product layer is removed from the sidewalls of the trench, exposing the deposited oxide layer and a surface portion of the semiconductor structure in the trench.