Semiconductor package and a method of fabricating the same
US11107769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Apr 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.