Integrated electrical/optical interface with two-tiered packaging

US11107770B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Suresh Ramalingam · Fremont, US
• Kun-Yung Chang · Los Altos Hills, US
• Yohan Frans · Palo Alto, US
• Chuan Xie · Fremont, US
• Mayank Raj · San Jose, US

Key dates

• Filing date: Jun 27, 2019
• Grant date: Aug 31, 2021
• Expiry date: Jun 27, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18161
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.