Method of manufacturing a three-dimensional non-volatile memory device
US11107829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Sep 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/40
Abstract
In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.