High voltage transistor structure
US11107916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Apr 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.