Majorana fermion quantum computing devices fabricated with ion implant methods
US11107965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/128
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.