Patterned silicide structures and methods of manufacture

US11107979B2 · kind B2 · utility

Assignee

• SPIN MEMORY, INC. · US

Inventors

• Kuk-Hwan Kim · Milpitas, US
• Dafna Beery · Palo Alto, US
• Marcin Gajek · Berkeley, US
• Michail Tzoufras · Sunnyvale, US
• Kadriye Deniz Bozdag · Sunnyvale, US
• Eric Michael Ryan · Fremont, US
• Satoru Araki · Chiba, JP
• Andy Walker · London, GB

Key dates

• Filing date: Dec 28, 2018
• Grant date: Aug 31, 2021
• Expiry date: Jan 15, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/324
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.