Resistive random access memory array and manufacturing method thereof
US11107983B2 · kind B2 · utility
2Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | Oct 1, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Oct 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/55
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RRAM array and its manufacturing method are provided. The RRAM array includes a substrate having an array region which has a first region and a second region. The RRAM array includes a bottom electrode layer on the substrate, an oxygen ion reservoir layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion reservoir layer, a resistance switching layer on the diffusion barrier layer, and a top electrode layer on the resistance switching layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.