Power optimization for memory subsystems
US11112982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.