Timed data transfer between a host system and a memory sub-system
US11113198B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 2020 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | May 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.