Post passivation interconnect
US11114395B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Oct 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device includes a first passivation layer over a substrate. The IC device further includes a redistribution line over the first passivation layer, wherein the redistribution line has a barrel-shaped profile. The IC device further includes a second passivation layer over the redistribution line. The IC device further includes a polymer layer over the second passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.