Semiconductor structure formation
US11114443B2 · kind B2 · utility
0Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.