Patent · US Active

Three-dimensional memory device with support structures in gate line slits and methods for forming the same

US11114458B2 · kind B2 · utility

1Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 31, 2019
Grant dateSep 7, 2021
Priority date
Expiry dateNov 15, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35

Abstract

Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.