Three-dimensional semiconductor memory devices having source structure overlaps buried insulating layer
US11114461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Dec 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.