Jeehoon Han
56Patents
3h-index
61Co-inventors
65Inventor score
Filing activity: Mar 7, 2014 → Jul 1, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10211154B2 | Three-dimensional semiconductor device | Electricity | 7 | Active |
| US11594544B2 | Semiconductor devices with string select channel for improved upper connection | Electricity | 3 | Active |
| US11404434B2 | Three-dimensional semiconductor memory device | Electricity | 3 | Active |
| US12120882B2 | Semiconductor device and electronic system including the same | Electricity | 2 | Active |
| US11404429B2 | Three-dimensional semiconductor memory devices | Electricity | 2 | Active |
| US11563023B2 | Semiconductor device with reduced vertical height | Electricity | 1 | Active |
| US11729972B2 | 3D memory devices | Electricity | 1 | Active |
| US11552098B2 | Semiconductor device including data storage pattern with improved retention characteristics | Electricity | 1 | Active |
| US11552099B2 | Vertical-type nonvolatile memory device including an extension area contact structure | Electricity | 1 | Active |
| US11049847B2 | Semiconductor device for preventing defects between bit lines and channels | Electricity | 1 | Active |
| US11374017B2 | Three-dimensional memory device including a string selection line gate electrode having a silicide layer | Electricity | 1 | Active |
| US11114461B2 | Three-dimensional semiconductor memory devices having source structure overlaps buried insulating layer | Electricity | 1 | Active |
| US11444098B2 | Vertical non-volatile memory devices and methods of programming the same | Electricity | 1 | Active |
| US11792994B2 | Three-dimensional memory device including a string selection line gate electrode having a silicide layer | Electricity | 1 | Active |
| US9171853B2 | Method of fabricating semiconductor device and device fabricated thereby | Electricity | 1 | Active |
| US11968836B2 | Three-dimensional semiconductor memory devices | Electricity | 1 | Active |
| US11616078B2 | Three-dimensional semiconductor memory devices having a source structure that overlaps a buried insulating layer | Electricity | 0 | Active |
| US11778834B2 | Three-dimensional (3D) semiconductor memory device | Electricity | 0 | Active |
| US12167598B2 | Three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same | Electricity | 0 | Active |
| US10396088B2 | Three-dimensional semiconductor device | Electricity | 0 | Active |
| US11791262B2 | Semiconductor device and data storage system including the same | Electricity | 0 | Active |
| US11925020B2 | Vertical semiconductor devices | Electricity | 0 | Active |
| US12354659B2 | Three-dimensional semiconductor memory device and electronic system including the same | Electricity | 0 | Active |
| US12058866B2 | Semiconductor device and electronic system | Electricity | 0 | Active |
| US9553098B2 | Semiconductor devices including separate line patterns | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.