Process for fabricating resistive memory cells
US11114614B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.