Method and apparatus for encoding and decoding data in memory system
US11115055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2019 |
| Grant date | Sep 7, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.