Method for forming semiconductor structure and overlay error estimation
US11119416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2019 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Oct 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/7065
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method includes forming a first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming an opening in the second dielectric layer by at least using an exposure tool; forming a second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, an overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.