Memory arrays and methods used in forming a memory array
US11120852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Feb 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.